A LOCal Oxidation of Silicon (LOCOS) method is widely used as an isolation method in semiconductor device fabrication. However, the LOCOS method may limit the quality of the electrical characteristics of semiconductor devices and high-integration, because it is typically susceptible to bird's beak phenomenon caused by lateral oxidation, crystalline defects in a silicon substrate caused by buffer layer stress, and redistribution of impurities ion-implanted for channel stop regions.
In order to avoid the above problems of the LOCOS method, shallow trench isolation (STI) methods have been proposed. In STI methods, a semiconductor substrate is typically etched to form a trench and the trench is then buried with an insulating material, and then chemical-mechanical polishing (CMP) is performed to form an isolation layer. In the STI method, the isolation layer may be formed without using a thermal oxidation step as in LOCOS, so that the adverse effects of the LOCOS method caused by thermal oxidation can be limited, and isolation layers appropriate for high integration can be formed.
However, in the conventional STI method, since the isolation layer is formed by a final chemical-mechanical polishing (CMP) step, a dishing phenomenon typically occurs and may cause the center of a trench isolation region to become concave. Dishing deteriorates the isolation characteristics of the trenches and generates poor planarization of adjacent active regions and layers subsequently formed thereon.